An enhanced key expansion module based on 2D hyper chaotic map and Galois field

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-11-05 DOI:10.1016/j.vlsi.2024.102302

Yafei Cao, Hongjun Liu

引用次数: 0

Abstract

Key expansion is an essential component in block cryptography, which serves the round function. By analyzing key expansion module of AES, it is found that the round-keys are highly correlated, and current round-key can be derived from its previous or the next round-key. To address these weaknesses, first, a 2D exponential chaotic map (2D-ECM) that exhibits ergodicity and superior randomness was constructed. Then, the Lyapunov exponents (LEs) were calculated based on the singular value decomposition (SVD) method. In addition, TestU01 test results showed that the sequences generated by 2D-ECM have better randomness. Further, an enhanced key expansion module was designed utilizing 2D-ECM and primitive polynomial over GF(2ⁿ), which has irreversibility and parallelism, and the round-keys are independent of each other. Simulation results and performance analysis demonstrated the effectiveness of the proposed enhanced key expansion module.

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基于二维超混沌图和加洛瓦场的增强型密钥扩展模块

密钥扩展是块密码学的重要组成部分，它具有轮询功能。通过分析 AES 的密钥扩展模块，可以发现轮密钥具有高度相关性，当前轮密钥可以从其上一轮或下一轮密钥中推导出来。针对这些弱点，首先构建了一种具有遍历性和超强随机性的二维指数混沌图（2D-ECM）。然后，根据奇异值分解（SVD）方法计算了李亚普诺夫指数（LE）。此外，TestU01 测试结果表明，2D-ECM 生成的序列具有更好的随机性。此外，利用 2D-ECM 和 GF(2n)上的基元多项式设计了一个增强型密钥扩展模块，该模块具有不可逆性和并行性，且圆密钥相互独立。仿真结果和性能分析表明了所提出的增强型密钥扩展模块的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.