Design and Demonstration of Array and Wallace-Tree Multiplier Families Using Adiabatic Quantum Flux Parametrons

Abstract

Adiabatic quantum-flux-parametron (AQFP) logic is an emerging superconducting circuit technology, which is superior in terms of energy dissipation at reasonable clock frequencies. Although multiplication is important for signal or image processing applications, such as fast Fourier transform processors or GPUs, no multipliers implemented in AQFP logic have been demonstrated yet. In this article, we introduce two types of algorithms to calculate multiplication results: array type and Wallace-tree type. We design 4-bit multipliers based on these algorithms using the AIST 10 kA/cm $^{2}$ high-speed standard process and compare these circuits in terms of the following metrics: number of Josephson junctions, circuit latency, area, and power dissipation. As a result, in all respects, the Wallace-tree type is better than the array type. In addition, we experimentally confirm that the fabricated chips containing both types of multipliers are operating correctly at 100 kHz for all test patterns, including random patterns. This is the first time AQFP multipliers have been experimentally demonstrated completely.