Experimental Demonstration of 1.2-Gb/s/Channel Readout Operation of Josephson–CMOS Hybrid Memory

Abstract

In this study, we aimed to achieve high-speed readout operations of Josephson–CMOS hybrid memory. We first experimentally evaluated the timing margin in the readout operations of the hybrid memory. In single-channel bit line measurements, we confirmed that the hybrid memory could work at a 1-GHz memory clock frequency with a timing margin as high as 0.63 ns. Subsequently, we designed and measured a Josephson–CMOS hybrid accumulator circuit to demonstrate high-speed read operations of the hybrid memory. The core design of the Josephson–CMOS hybrid memory follows our previous design. We introduced a sequential-access read-only CMOS memory and a single-flux-quantum accumulator into a test circuit, enabling high-speed measurement of Josephson–CMOS hybrid memory with only two high-speed external inputs. We designed and fabricated a test circuit using the Rohm 180-nm CMOS process and the AIST-ADP2 Josephson process. In the measurement, we achieved correct operation of the test circuit, including the readout operation of the 32-b hybrid memory at a memory clock frequency as high as 1.2 GHz, corresponding to a 38.4-Gb/s readout.