Direct Digital Simultaneous Phase-Amplitude Noise and Allan Deviation Measurement System

Marco Pomponio;Archita Hati;Craig Nelson
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Abstract

In this paper, we present a direct digital measurement system capable of simultaneously measuring phase noise, amplitude noise, and Allan deviation with and without cross-correlation. The residual phase noise of the single-channel system achieves $\mathscr {L}\left ({{1 \text {Hz}}}\right)~ \textrm {=} -143 \text {dBc/Hz}$ for a 10 MHz input signal and an Allan deviation noise floor of $3.2 \times 10^{-15}$ at 1 second averaging time ( $\tau $ ). The system’s performance improves as expected with cross-correlation, resulting in an average-limited residual white noise floor of −185 dBc/Hz after only a few minutes of averaging, an improvement of 30 dB compared to a single-channel system. It also reaches an average limited flicker phase noise floor of $\mathscr {L}\left ({{1 \text {Hz}}}\right) ~\textrm {=} -160 \text {dBc/Hz}$ within two days, with an Allan deviation of $5 \times 10^{-16}$ @ $\tau ~\textrm {=}1 \text {second}$ . To our knowledge, this represents the lowest noise performance ever reported for a digital measurement system. Our solution is based on a pair of high-performance analog-to-digital converters and a single system-on-a-chip (SoC) with multiple processors and a field programmable gate array (FPGA). The architecture allows for processing all data samples in real-time without dead-time between calculation frames, enabling the fastest averaging possible during cross-correlation.
直接数字同步相位振幅噪声和阿伦偏差测量系统
在本文中,我们介绍了一种直接数字测量系统,该系统能够同时测量相位噪声、振幅噪声和阿伦偏差(有无交叉相关)。单通道系统的残余相位噪声达到 $\mathscr {L}\left ({{1 \text {Hz}}\right)~ \textrm {=}对于 10 MHz 输入信号,-143 \text {dBc/Hz}$;在 1 秒平均时间($\tau $)下,阿伦偏差噪声本底为 3.2 \times 10^{-15}$。该系统的性能随着交叉相关性的提高而提高,仅在几分钟的平均时间后,平均限制残余白噪声本底就达到了 -185 dBc/Hz,与单通道系统相比提高了 30 dB。它的平均有限闪烁相位噪声本底也达到了 $\mathscr {L} ({{1 \text {Hz}}} (right) ~\textrm {=}-160(文本{dBc/Hz}}$ 在两天内,阿伦偏差为 5 (times 10^{-16}$ @ $\tau ~\textrm {=}1 (文本{秒}}$ 。据我们所知,这是迄今为止报告的数字测量系统中噪音最低的性能。我们的解决方案基于一对高性能模数转换器和一个带有多个处理器和现场可编程门阵列(FPGA)的单芯片系统(SoC)。该架构可实时处理所有数据样本,计算帧之间没有死区时间,从而在交叉相关过程中实现最快的平均。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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