EASTER: Learning to Split Transformers at the Edge Robustly

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Xiaotian Guo;Quan Jiang;Yixian Shen;Andy D. Pimentel;Todor Stefanov
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引用次数: 0

Abstract

Prevalent large transformer models present significant computational challenges for resource-constrained devices at the Edge. While distributing the workload of deep learning models across multiple edge devices has been extensively studied, these works typically overlook the impact of failures of edge devices. Unpredictable failures, due to, e.g., connectivity issues or discharged batteries, can compromise the reliability of inference serving at the Edge. In this article, we introduce a novel methodology, called EASTER, designed to learn robust distribution strategies for transformer models against device failures that consider the tradeoff between robustness (i.e., maintaining model functionality against failures) and resource utilization (considering memory usage and computations). We evaluate EASTER with three representative transformers—ViT, GPT-2, and Vicuna—under device failures. Our results demonstrate EASTER’s efficiency in memory usage, and possible end-to-end latency improvement for inference across multiple edge devices while preserving model accuracy as much as possible under device failures.
EASTER: 学习在边缘稳健地拆分变压器
普遍存在的大型变压器模型给资源有限的边缘设备带来了巨大的计算挑战。虽然在多个边缘设备上分配深度学习模型的工作量已经得到了广泛的研究,但这些研究通常忽略了边缘设备故障的影响。由于连接问题或电池放电等原因造成的不可预测的故障,会损害边缘推理服务的可靠性。在本文中,我们介绍了一种名为 EASTER 的新方法,该方法旨在学习针对设备故障的变压器模型稳健分布策略,其中考虑了稳健性(即针对故障保持模型功能)和资源利用率(考虑内存使用和计算)之间的权衡。我们用三个具有代表性的变压器--ViT、GPT-2 和 Vicuna 评估了设备故障下的 EASTER。我们的结果证明了 EASTER 在内存使用方面的效率,以及在设备故障情况下尽可能保持模型准确性的同时,在跨多个边缘设备进行推理时可能改善的端到端延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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