An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver

Abstract

This brief introduces a multi-level phase-change memory (PCM) readout circuit that realizes a true M-metric readout scheme that inherently has a wide dynamic input range. In order to overcome the limited readout speed of a basic M-metric scheme that draws a small current through a PCM cell over a large bit-line capacitance and senses the voltage, we propose an opamp-less M-metric readout circuit that drives the bit-line in a successive approximation manner with a comparator-based push-pull driver (CPPD). The bit-line driving speed of the proposed readout circuit is comparable with that of a conventional voltage driver, but the power consumption is greatly reduced owing to the absence of a power hungry opamp. The prototype design achieves a full 6-bit linearity and 245-uW power consumption at a 270-ns readout speed.