An improved 4H-SiC trench MOS barrier Schottky diode with current spreading layer and low resistance layer

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-10-24 DOI:10.1016/j.mejo.2024.106451

Hai-tao Ge , Wang-zi-xuan Zhen , Cheng-hao Yu , Masayuki yamamoto , Wen-sheng Zhao , Hao-min Guo , Xiao-dong Wu

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引用次数: 0

Abstract

This paper investigates an improved trench MOS barrier Schottky (TMBS) structure with extra double epitaxial layers (DE-TMBS) based on the conventional TMBS (C-TMBS) featuring a high-doped N-type current spreading layer (CSL) and a high-doped low resistance layer (LRL). Compared to the C-TMBS, the CSL in the improved structure is grown on the N-type drift region, and the LRL is extended on the CSL. According to the numerical simulations and analytical models, the specific on-resistance (R_on,sp) of DE-TMBS can be significantly reduced compared to the conventional one. This is primarily due to the high doping concentration in CSL, which effectively lowers both the JFET resistance and spreading resistance. Additionally, the increased doping concentration in LRL reduces the channel resistance and JFET resistance. Moreover, the doping concentration and thickness of CSL and LRL are optimized to maximize the figure of merit (FOM), that R_on,sp is reduced by 40.9 % and the FOM (BV²/R_on,sp) is improved by 67.9 % compared to the C-TMBS structure.

查看原文本刊更多论文

带有电流扩散层和低阻层的改进型 4H-SiC 沟槽 MOS 势垒肖特基二极管

本文在传统 TMBS（C-TMBS）的基础上，研究了一种具有额外双外延层（DE-TMBS）的改进型沟槽 MOS 势垒肖特基（TMBS）结构，其特点是具有一个高掺杂 N 型扩流层（CSL）和一个高掺杂低阻层（LRL）。与 C-TMBS 相比，改进结构中的 CSL 生长在 N 型漂移区上，而 LRL 则延伸到 CSL 上。根据数值模拟和分析模型，DE-TMBS 的比导通电阻（Ron,sp）比传统结构显著降低。这主要是由于 CSL 中的高掺杂浓度有效降低了 JFET 电阻和展宽电阻。此外，LRL 中掺杂浓度的增加也降低了沟道电阻和 JFET 电阻。此外，与 C-TMBS 结构相比，CSL 和 LRL 的掺杂浓度和厚度得到了优化，从而最大限度地提高了优点系数（FOM），Ron,sp 降低了 40.9%，FOM（BV2/Ron,sp）提高了 67.9%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.