Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency

Abstract

High-speed, low-power consumption, compact area, and high resolution are critical for analog/mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.