A lightweight dual-link accelerated authentication protocol based on NLFSR-XOR APUF

Abstract

Physical Unclonable Function (PUF) circuits, as a lightweight hardware security primitive, can provide reliable authentication for resource-constrained Internet of Things (IoT) devices. However, in real-time environments and systems, authentication of embedded devices has strict requirements on resources and low latency. Therefore, this paper proposes a lightweight dual-link accelerated authentication protocol design based on NLFSR-XOR APUF, through the study of Non-Linear Feedback Shift Registers (NLFSR) and XOR APUF circuits. First, the scheme utilizes the symmetric path delay deviation characteristics of APUF and the complexity of NLFSR state transitions to form a nonlinear output function that changes with the challenge signal. Then, a lightweight and attack-resistant authentication protocol is established by combining the random probability of shuffling array bits with the XOR confusion mechanism. Finally, the advantages of GPU parallel computing and AES T-table reconfiguration scheme are used to achieve an accelerated and side-channel attack-resistant authentication protocol. Experimental results show that the PUF circuit can effectively resist various modeling attacks, including logistic regression (LR), artificial neural network (ANN), and support vector machine (SVM). The security of the protocol has been formally verified, and the prototype has been implemented on the Xilinx xc100T development board, effectively resisting deception attacks, physical attacks, and modeling attacks. The protocol's area overhead in terms of LUT and encryption time is reduced by 58.6 % and 67.8 %, respectively, compared to similar protocols.