S. Manikandan, P. Suveetha Dhanaselvam, M. Karthigai Pandian
{"title":"Subthreshold Drain Current Model of Cylindrical Gate All-Around Junctionless Transistor With Three Different Gate Materials","authors":"S. Manikandan, P. Suveetha Dhanaselvam, M. Karthigai Pandian","doi":"10.1002/jnm.3312","DOIUrl":null,"url":null,"abstract":"<div>\n \n <p>A novel subthreshold drain current model has been developed for a cylindrical gate all-around junctionless transistor with three different gate materials. The proposed device is built with three gate regions of different work functions that effectively reduce the short-channel effects caused by quantum mechanical effects. The drain current equation is solved for all three operating regions to investigate the device switching characteristics and minimize the drain-induced barrier lowering (DIBL), velocity saturation, mobility degradation, and tunneling. It is understood that the triple material gate structure enhances the transport efficiency of the device. The proposed analytical model is validated by comparison with Sentaurus TCAD numerical simulator results and good agreement is found to be achieved.</p>\n </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":null,"pages":null},"PeriodicalIF":1.6000,"publicationDate":"2024-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1002/jnm.3312","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel subthreshold drain current model has been developed for a cylindrical gate all-around junctionless transistor with three different gate materials. The proposed device is built with three gate regions of different work functions that effectively reduce the short-channel effects caused by quantum mechanical effects. The drain current equation is solved for all three operating regions to investigate the device switching characteristics and minimize the drain-induced barrier lowering (DIBL), velocity saturation, mobility degradation, and tunneling. It is understood that the triple material gate structure enhances the transport efficiency of the device. The proposed analytical model is validated by comparison with Sentaurus TCAD numerical simulator results and good agreement is found to be achieved.
期刊介绍：
Prediction through modelling forms the basis of engineering design. The computational power at the fingertips of the professional engineer is increasing enormously and techniques for computer simulation are changing rapidly. Engineers need models which relate to their design area and which are adaptable to new design concepts. They also need efficient and friendly ways of presenting, viewing and transmitting the data associated with their models.
The International Journal of Numerical Modelling: Electronic Networks, Devices and Fields provides a communication vehicle for numerical modelling methods and data preparation methods associated with electrical and electronic circuits and fields. It concentrates on numerical modelling rather than abstract numerical mathematics.
Contributions on numerical modelling will cover the entire subject of electrical and electronic engineering. They will range from electrical distribution networks to integrated circuits on VLSI design, and from static electric and magnetic fields through microwaves to optical design. They will also include the use of electrical networks as a modelling medium.
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