CMOS-compatible strain engineering for monolayer semiconductor transistors

Abstract

Strain engineering has played a key role in modern silicon electronics, having been introduced as a mobility booster in the 1990s and commercialized in the early 2000s. Achieving similar advances with two-dimensional (2D) semiconductors in a complementary metal–oxide–semiconductor (CMOS)-compatible manner could improve the industrial viability of 2D material transistors. Here, we show that silicon nitride capping layers can impart strain to monolayer molybdenum disulfide (MoS2) transistors on conventional silicon substrates, improving their performance with a CMOS-compatible approach, at a low thermal budget of 350 °C. Strained back-gated and dual-gated MoS2 transistors exhibit median increases in on-state current of up to 60% and 45%, respectively. The greatest improvements are found when reducing both transistor channels and contacts from micrometre-scale to 200 nm, reaching saturation currents of 488 µA µm−1 in devices with just 400 nm contact pitch. Simulations show that the performance enhancement is mainly due to tensile strain lowering the contact Schottky barriers, and that further reducing device dimensions, including contacts, could lead to additional increases in strain and performance. The on-current performance of MoS2-based transistors can be improved by using silicon nitride capping layers that apply strain to the devices.