Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC

IF 4.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-18 DOI:10.1109/jssc.2024.3472023

Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce Fleischer, Joshua Rubin, JohnDavid Lancaster, Saekyu Lee, Matthew Cohen, Matthew Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey K. Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Röwer, David Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tèllez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang

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在 5 纳米人工智能 SoC 中使用软件辅助峰值电流调节方案优化功率限制推理性能

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.