Exploring thermal effects of advanced backside power delivery network beyond 3 nm node

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-10-15 DOI:10.1016/j.mejo.2024.106440

Haoyu Zhang , Linlin Cai , Haifeng Chen , Binyu Yin , Wangyong Chen

{"title":"Exploring thermal effects of advanced backside power delivery network beyond 3 nm node","authors":"Haoyu Zhang , Linlin Cai , Haifeng Chen , Binyu Yin , Wangyong Chen","doi":"10.1016/j.mejo.2024.106440","DOIUrl":null,"url":null,"abstract":"<div><div>Backside Power Delivery Networks (BSPDNs) address scaling issues by relocating power, boosting efficiency and density. However, thermal effects pose challenges. In this work, a comprehensive thermal analysis of BSPDN is performed to elaborate the key modulation factors and possible optimization approaches, where the specific backside metal layers are constructed to investigate the impacts of operating conditions, via distribution and materials on thermal effects. To improve the simulation efficiency, the effective thermal conductivity is employed to simplify the Nanosheet (NSH) FET based front-end-of-line (FEOL) and other layers at the 3 nm technology node. Results show that non-uniform via distribution in BSPDN causes temperature fluctuations, but augmenting Backside Via counts effectively mitigates local peak temperature increases from higher power. For BSPDN, backside cooling solutions outperform frontside in efficiency, particularly at high via densities. Using high thermal conductivity inter-metal dielectric (IMD) materials significantly reduces global temperature rise and fluctuations from non-uniform vias in BSPDN, enhancing PDN design flexibility.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001449","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

Backside Power Delivery Networks (BSPDNs) address scaling issues by relocating power, boosting efficiency and density. However, thermal effects pose challenges. In this work, a comprehensive thermal analysis of BSPDN is performed to elaborate the key modulation factors and possible optimization approaches, where the specific backside metal layers are constructed to investigate the impacts of operating conditions, via distribution and materials on thermal effects. To improve the simulation efficiency, the effective thermal conductivity is employed to simplify the Nanosheet (NSH) FET based front-end-of-line (FEOL) and other layers at the 3 nm technology node. Results show that non-uniform via distribution in BSPDN causes temperature fluctuations, but augmenting Backside Via counts effectively mitigates local peak temperature increases from higher power. For BSPDN, backside cooling solutions outperform frontside in efficiency, particularly at high via densities. Using high thermal conductivity inter-metal dielectric (IMD) materials significantly reduces global temperature rise and fluctuations from non-uniform vias in BSPDN, enhancing PDN design flexibility.

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探索 3 纳米节点之后先进背面功率传输网络的热效应

背面功率传输网络（BSPDN）通过重新定位功率、提高效率和密度来解决扩展问题。然而，热效应带来了挑战。在这项工作中，对 BSPDN 进行了全面的热分析，以阐述关键的调制因素和可能的优化方法，其中构建了特定的背面金属层，以研究工作条件、通孔分布和材料对热效应的影响。为了提高仿真效率，采用了有效热导率来简化基于纳米片（NSH）场效应晶体管的前端（FEOL）和 3 纳米技术节点上的其他层。结果表明，BSPDN 中不均匀的通孔分布会导致温度波动，但增加背面通孔数量可有效缓解较高功率带来的局部峰值温度上升。对于 BSPDN，背面冷却解决方案的效率优于正面冷却解决方案，尤其是在高通孔密度的情况下。使用高导热金属间介质 (IMD) 材料可显著降低 BSPDN 中不均匀通孔造成的整体温升和波动，从而提高 PDN 设计的灵活性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.