A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Annu Dabas , Shweta Kumari , Maneesha Gupta , Richa Yadav
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引用次数: 0

Abstract

In this work, a novel fully differential two stage class AB Recycling Folded Cascode Operational Transconductance Amplifier (RFC OTA) using Differential Flipped Voltage Follower (DFVF) has been proposed. The DFVF and Dynamic Threshold Metal Oxide Semiconductor (DTMOS) transistors have been used as differential input stage of the proposed RFC OTA. These techniques provide enhancement in gain and bandwidth of the proposed OTA. To further improve the performance of proposed circuit, positive feedback at current mirror load along with Hybrid Cascode compensation have been implemented. A common source (CS) amplifier has been used between gate and source terminals of differential input stage which further boosts the transconductance. The proposed RFC OTA is designed and simulated using 180 nm CMOS technology with load capacitance of 10 pF. It provides an excellent dc gain of 112.61 dB and gain bandwidth product (GBW) of 25.88 MHz along with 88.140 phase margin. The proposed circuit dissipates 124.66 μW of power at ± 0.5V supply voltage. The Monte Carlo analysis against device mismatch has also been performed to prove robustness of the proposed circuit.
采用 DFVF 和混合级联补偿技术设计的新型高性能全差分两级 RFC OTA 架构
本研究提出了一种使用差分翻转电压跟随器(DFVF)的新型全差分两级 AB 类回收折叠级联运算跨导放大器(RFC OTA)。DFVF 和动态阈值金属氧化物半导体(DTMOS)晶体管被用作拟议 RFC OTA 的差分输入级。这些技术提高了拟议 OTA 的增益和带宽。为了进一步提高拟议电路的性能,在电流镜负载上实施了正反馈以及混合级联补偿。在差分输入级的栅极和源极之间使用了共源(CS)放大器,从而进一步提高了跨导。拟议的 RFC OTA 采用 180 nm CMOS 技术设计和仿真,负载电容为 10 pF。它的直流增益高达 112.61 dB,增益带宽积 (GBW) 为 25.88 MHz,相位裕度为 88.140。在 ± 0.5V 电源电压下,拟议电路的耗散功率为 124.66 μW。此外,还针对器件失配进行了蒙特卡罗分析,以证明所提电路的稳健性。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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