Hardware acceleration of Tiny YOLO deep neural networks for sign language recognition: A comprehensive performance analysis

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-09-26 DOI:10.1016/j.vlsi.2024.102287

Mohita Jaiswal, Abhishek Sharma, Sandeep Saini

引用次数: 0

Abstract

In this paper, we benchmark two automation frameworks, Vitis AI and FINN, for sign language recognition on a Field Programmable Gate Array (FPGA). We conducted an in-depth exploration of both frameworks using Tiny YOLOv2 networks by varying design parameters such as precision, parallelism ratio, etc. Further, a fair baseline comparison is made based on accuracy, speed, and hardware resources. Experimental findings demonstrate that the Vitis AI outperforms the FINN framework and traditional GPU and CPU platforms by achieving significant improvements of 1.08x, 1.7x, and 2.9x in terms of latency. Leveraging Vitis AI, our system achieved a detection speed of 32.7 frames per second (FPS) on the Kria KV260 FPGA with a power consumption rate of 5.6 W and an impressive mean Average Precision (mAP) score of 61.2% on the Hindi Indian Sign Language (ISL) dataset.

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用于手语识别的 Tiny YOLO 深度神经网络的硬件加速：综合性能分析

在本文中，我们在现场可编程门阵列（FPGA）上对 Vitis AI 和 FINN 这两个自动化框架进行了手语识别基准测试。我们使用 Tiny YOLOv2 网络，通过改变精度、并行比等设计参数，对这两个框架进行了深入探讨。此外，我们还根据精度、速度和硬件资源进行了公平的基线比较。实验结果表明，Vitis AI 的性能优于 FINN 框架以及传统的 GPU 和 CPU 平台，在延迟方面分别显著提高了 1.08 倍、1.7 倍和 2.9 倍。利用 Vitis AI，我们的系统在 Kria KV260 FPGA 上实现了每秒 32.7 帧 (FPS) 的检测速度，功耗仅为 5.6 W，在印地语印度手语 (ISL) 数据集上取得了 61.2% 的平均精确度 (mAP) 高分。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.