Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-09-27 DOI:10.1016/j.mejo.2024.106428

Zhengfeng Huang , Xin Chen , Xinyu Jiang , Lei Ai , Huaguo Liang , Yiming Ouyang , Tianming Ni

{"title":"Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process","authors":"Zhengfeng Huang , Xin Chen , Xinyu Jiang , Lei Ai , Huaguo Liang , Yiming Ouyang , Tianming Ni","doi":"10.1016/j.mejo.2024.106428","DOIUrl":null,"url":null,"abstract":"<div><div>As integrated circuit technology continues to shrink, single-event multiple-node-upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposes two quadruple-node-upset hardened latches: 4DICE-C and 4DICE-V. These two latches are both based on dual-interlocked-storage-cell (DICE) that can achieve single-node-upset self-recovery. Besides, a quadruple-modular redundancy fault-tolerant mechanism is constructed. The 4DICE-C uses the clocked quadruple-input C-element at the output stage, the 4DICE-V uses clocked voter at the output stage. Compared with previous hardened latches containing C-elements, the 4DICE-V is less sensitive to high impedance state and can efficiently tolerate soft errors at internal nodes. In addition, compared with previous single-event triple-node-upset and quadruple-node-upset hardened latches, the 4DICE-C latch has achieved 100 % tolerance efficiency of single-event quadruple-node-upset, the best delay overhead and APDP comprehensive overhead, 18.69 % lower than average delay.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001322","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

As integrated circuit technology continues to shrink, single-event multiple-node-upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposes two quadruple-node-upset hardened latches: 4DICE-C and 4DICE-V. These two latches are both based on dual-interlocked-storage-cell (DICE) that can achieve single-node-upset self-recovery. Besides, a quadruple-modular redundancy fault-tolerant mechanism is constructed. The 4DICE-C uses the clocked quadruple-input C-element at the output stage, the 4DICE-V uses clocked voter at the output stage. Compared with previous hardened latches containing C-elements, the 4DICE-V is less sensitive to high impedance state and can efficiently tolerate soft errors at internal nodes. In addition, compared with previous single-event triple-node-upset and quadruple-node-upset hardened latches, the 4DICE-C latch has achieved 100 % tolerance efficiency of single-event quadruple-node-upset, the best delay overhead and APDP comprehensive overhead, 18.69 % lower than average delay.

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在 32 纳米工艺中设计具有低延迟和四节点上移容差的辐射加固锁存器

随着集成电路技术的不断发展，电荷共享效应引起的单事件多节点重置已成为影响芯片可靠性的一个重要因素。本文提出了两种四重节点重置加固锁存器：4DICE-C 和 4DICE-V。这两种锁存器都基于双互锁存储单元（DICE），可实现单节点自恢复。此外，还构建了四重模块冗余容错机制。4DICE-C 在输出级使用时钟四重输入 C 元件，4DICE-V 在输出级使用时钟表决器。与以往含有 C 元素的加固锁存器相比，4DICE-V 对高阻抗状态的敏感性更低，可以有效地容忍内部节点的软错误。此外，与之前的单事件三节点上集和四节点上集加固锁存器相比，4DICE-C 锁存器实现了 100 % 的单事件四节点上集容错效率、最佳延迟开销和 APDP 综合开销，比平均延迟低 18.69 %。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.