{"title":"PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST","authors":"Kannan R , Vidhya K","doi":"10.1016/j.vlsi.2024.102289","DOIUrl":null,"url":null,"abstract":"<div><div>Reversible logic has gained popularity recently because it allows circuits to use significantly less power. Due to the inherent reversibility of quantum operation, there is enormous interest in designing and optimizing reversible circuits. In this work, a new gate named as transvidkan gate, Quantum Random Reversible Flip Flop, Sequence generator, and Build in Self-Test (BIST) has been proposed. Quantum Random Reversible Flip Flop (QRRFF) is an emerging technology that is used in a variety of apps that use modern security and encryption systems. For creating a random string, typical approaches combine an entropy source with an elimination or bit-generation system. Quantum computing reversible logic chips and Low-power design are emerging as intriguing research topics. A classical logic-based 8-bit reversible comparator is represented using existing reversible gates. This study provides a BIST-based architecture for a comparator design that reduces the garbage outputs, quantum cost, and constant inputs. According to simulation result, the proposed approach outperforms traditional methods in terms of hardware complexity and quantum cost.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102289"},"PeriodicalIF":2.2000,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926024001536","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Reversible logic has gained popularity recently because it allows circuits to use significantly less power. Due to the inherent reversibility of quantum operation, there is enormous interest in designing and optimizing reversible circuits. In this work, a new gate named as transvidkan gate, Quantum Random Reversible Flip Flop, Sequence generator, and Build in Self-Test (BIST) has been proposed. Quantum Random Reversible Flip Flop (QRRFF) is an emerging technology that is used in a variety of apps that use modern security and encryption systems. For creating a random string, typical approaches combine an entropy source with an elimination or bit-generation system. Quantum computing reversible logic chips and Low-power design are emerging as intriguing research topics. A classical logic-based 8-bit reversible comparator is represented using existing reversible gates. This study provides a BIST-based architecture for a comparator design that reduces the garbage outputs, quantum cost, and constant inputs. According to simulation result, the proposed approach outperforms traditional methods in terms of hardware complexity and quantum cost.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.