Radiation-hardened latch design with triple-node-upset recoverability

Abstract

As CMOS technology scales down the susceptibility of integrated circuits to radiation effects makes them vulnerable to single-event upsets (SEUs) that may cause the formation of soft errors. In nanometer technologies, SEUs have the potential to impact many nodes within a circuit, resulting to Multiple Node Upsets (MNUs). Several techniques have been proposed to deal with SEUs that simultaneously influence either one, two, or three nodes. This paper presents a latch design that is capable of tolerating up to triple-node upsets (TNUs). Hardware redundancy is exploited to store data in many nodes inside the latch, along with a multiple feedback scheme that provides the recovery of the correct latch state in the case of SEUs. The proposed method provides faster recovery time after an SEU, and at the same time reduced power-delay and area-power-delay products with respect to existing solutions in the literature.