Junctionless accumulation-mode SOI ferroelectric FinFET for synaptic weights

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-09-18 DOI:10.1016/j.mejo.2024.106413

Roopesh Singh, Sushant Mittal, Shivam Verma

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引用次数: 0

Abstract

In this work, a novel silicon-on-insulator (SOI) based junctionless-accumulation-mode (JAM) ferroelectric (FE) fin field effect transistor (FinFET) is proposed along with its fabrication process flow at a 3-nm node for synaptic weights. The proposed JAM FE FinFET device can be easily integrated with the fabrication flow of p-FinFET in SOI process flow. The proposed device can be easily incorporated into standard FinFET SOI technology and thus is very attractive with respect to previously proposed devices. Further, using a well-calibrated 3D TCAD simulation setup, we show that the device effectively replicates the behavior required for neuromorphic computing applications. The outcomes of the proposed study emphasize the significance of using the JAM FE FinFET as a synaptic weight device that exhibits a 76 % higher nonvolatile conductance range in the ON-state over existing junctionless and conventional FE FinFET devices. Our simulations show that the proposed device offers continuous linear conductance variation and symmetric switching characteristics, which are essential for neuromorphic applications.

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用于突触权重的无结积模 SOI 铁电 FinFET

本研究提出了一种基于硅绝缘体（SOI）的新型无结堆积模式（JAM）铁电鳍场效应晶体管（FinFET），以及用于突触砝码的 3 纳米节点制造工艺流程。所提出的 JAM FE FinFET 器件可与 SOI 工艺流程中的 p-FinFET 制造流程轻松集成。所提出的器件可以很容易地集成到标准的 FinFET SOI 技术中，因此与之前提出的器件相比非常具有吸引力。此外，通过使用校准良好的三维 TCAD 仿真设置，我们表明该器件有效地复制了神经形态计算应用所需的行为。我们提出的研究成果强调了使用 JAM FE FinFET 作为突触加权器件的重要性，该器件在导通状态下的非易失性电导范围比现有的无结器件和传统 FE FinFET 器件高出 76%。我们的模拟显示，所提出的器件具有连续线性电导变化和对称开关特性，这对于神经形态应用至关重要。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.