A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements

Abstract

With the continuous reduction of feature size of transistors, single-event triple-node-upsets (TNUs) induced by the striking of radiation particles in nano-scale CMOS circuits have emerged as a significant reliability concern. To address the shortcomings of existing radiation-hardened designs, including low reliability and high overhead, this paper proposes a cost-effective and highly robust TNU self-recovery latch design called DOCTRL. The proposed DOCTRL latch primarily consists of six dual-output C-elements (DOCs) and two clocked DOCs. By utilizing DOCs with two independent outputs, the proposed DOCTRL latch achieves a smaller area overhead. In addition, a four-level circular interlock matrix connection is designed to recover all possible TNUs within the proposed DOCTRL latch. Meanwhile, the latch also incorporates clock gating technology and a high-speed path to minimize power consumption and delay penalties. Simulation results indicate that the proposed DOCTRL reduces area by an average of 32.43 %, power consumption by 46.84 %, delay by 14.43 %, and area-power-delay product (APDP) by 69.55 %, compared to the five typical TNU self-recovery latches (SCLCRL, TNUSH, LCTNUCR, ADTRL, TSRL). Furthermore, detailed process, voltage, temperature (PVT), and Monte Carlo simulations verify the robustness of the proposed DOCTRL latch.