Normalized signature graph of analog circuits for fault classification using digital testing

Abstract

This paper presents the power-on signature graph of analog circuits for fault classification. This graph can be attained using the simulation mechanism through the practical circuit simulator and the hardware mechanism through the mixed-signal design. The presented signature graph is influenced by changes in pass-band transmission and bandwidth as a result of device under test (DUT) component modifications. In order to exercise the frequency band of the DUT for fault stimulation, sinusoidal waveforms wiped at their frequencies are produced using the analog waveform generator (AWG). The analog compactor is devised to accumulate the output samples from the DUT for signature generation, compared with global signature boundaries derived from the worst-case analysis. The built-in self-test controller is devised to properly synchronize the process of analog test cycle for proper signature generation. Two DUTs chosen from a variety of analog circuits in frequency bands used in medical applications are subjected to this testing mechanism. Due to the difference between the wiped sinusoidal frequencies of the AWG in the simulation mechanism and the hardware mechanism, the normalized signature graphs of each component in DUTs using both mechanisms are developed to attain the approved convergences between the two mechanisms.