FPGA-based implementation and verification of hybrid security algorithm for NoC architecture

Abstract

Networks on Chip (NoCs) are a crucial component in modern System on Chips (SoCs), which provide the communication infrastructure for various processing elements such as CPUs, GPUs, DSPs, and other IPs. As a result, security is a critical aspect of NoCs, and it is essential to protect them from various security threats such as information leakage, denial of service attacks, and unauthorized access. The communication over NoCs carries sensitive and confidential information, which needs to be protected from unauthorized access, interception, or tampering. A Hybrid Secure technique is proposed in this research paper to protect the data during NoC transmission. The Noekeon and RSA algorithms are combined to create the hybrid secure algorithm for NoC architecture. The Noekeon algorithm provides a high level of security, efficiency, flexibility, and resistance to side-channel attacks, making it an ideal choice for securing communication in NoC and other applications. The RSA encryption algorithm is modified to minimize the number of calculations. The proposed hybrid secure algorithm is tested on 4 × 4 2D mesh NoC architecture. The average throughput of the proposed algorithm is increased to 64% and 51% latency is reduced when compared to existing research work.