A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices

IF 4.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2024-09-17 DOI:10.1109/JSSC.2024.3414159

Xiaodong Meng;Xing Li;Chi-Ying Tsui;Wing-Hung Ki;Weiqiang Liu

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引用次数: 0

Abstract

A primary driver with a fractional capacitance (FC) auto-tuning loop (ATL) for wireless-powered biomedical devices is presented. The proposed ATL maintains the resonance of the primary LC tank against varying inductance over a wide range in real time. The analog ATL has a wide loop bandwidth and achieves phase locking within six cycles. The fractional capacitor is realized with a switch-controlled capacitor. By varying the turn-on time of the switch, the effective capacitance is changed, which tunes the resonant frequency of the primary LC tank. The primary driver is a full-bridge Class-D power amplifier (PA). High-side NMOS power switches are driven by bootstrap circuits. An adaptive offset controller is proposed to compensate for the delays of comparators to enhance tuning accuracy. The chip is fabricated using a 0.18-

$\mu $

m bipolar-CMOS-DMOS (BCD) process, and the active area is 0.66 mm2. The system operates at 13.56 MHz and maintains both zero-voltage switching (ZVS) and zero-current switching (ZCS) in a steady state. The maximum PA output power is 200 mW, the measured tuning range is 31.5%, and the tuning error is 1.89 ns.

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用于无线供电植入式医疗设备的带分数电容自动调谐回路的 13.56-MHz 初级驱动器

本文介绍了一种带有分数电容（FC）自动调谐回路（ATL）的初级驱动器，适用于无线供电的生物医学设备。所提出的 ATL 可在大范围内实时保持初级 LC 罐的共振，以应对电感的变化。模拟 ATL 具有较宽的环路带宽，可在六个周期内实现锁相。小数电容器由开关控制电容器实现。通过改变开关的导通时间，可以改变有效电容，从而调整初级 LC 罐的谐振频率。主驱动器是一个全桥 D 类功率放大器（PA）。高压侧 NMOS 功率开关由自举电路驱动。芯片采用自适应偏移控制器来补偿比较器的延迟，从而提高调谐精度。该芯片采用 0.18- $\mu $ m 双极-CMOS-DMOS (BCD) 工艺制造，有效面积为 0.66 mm2。该系统工作频率为 13.56 MHz，在稳定状态下保持零电压开关（ZVS）和零电流开关（ZCS）。功率放大器的最大输出功率为 200 mW，测量的调谐范围为 31.5%，调谐误差为 1.89 ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.