Design and investigation of electrostatic doped heterostructure vertical Si(1-x)Gex/Si nanotube TFET

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-09-13 DOI:10.1016/j.mejo.2024.106417

Soumya Sen, Mamta Khosla, Ashish Raman

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引用次数: 0

Abstract

Researchers are inclining toward heterostructures suitable lattice matching, in Tunnel FETs to eliminate the difficulties of decreased On-Current, subthreshold swings, and ambipolar behavior. Nowadays, Electrostatic doping (ED) is a scrutinized substitute device for creating areas with a high electron or hole density to the conventional doped devices. This manuscript proposes an Electrostatic Doped Heterostructure Vertical Si_(1-x)Ge_x/Si Nanotube Tunnel Field Effect with performance scanned by analyzing the different device parameters, considering the energy band diagram, concentrations of electrons, holes, potential, and electric field. In comparison to the Nanowire TFETs, the area, and rate of tunneling of the proposed device stand superior with a better I_ON/I_OFF ratio of 1.56∗10¹³ and a lower OFF-current of about ∼10⁻¹⁸A/μm. The device exhibits a Drain current (I_DS) of 2.39∗10⁵A/μm. The architecture of the suggested device possessing Si(1-x)Gex/Si structure exhibits enhanced characteristics like improved steepness of the sub-threshold slope, I_ON/I_OFF ratio, drain current, and lowered OFF-current.

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静电掺杂异质结构垂直硅（1-x）Gex/硅纳米管 TFET 的设计与研究

研究人员倾向于在隧道式场效应晶体管中采用适合晶格匹配的异质结构，以消除导通电流下降、阈下波动和伏极行为等难题。如今，静电掺杂（ED）已成为一种备受关注的替代器件，它能在传统掺杂器件的基础上创造出具有高电子或空穴密度的区域。本手稿提出了一种静电掺杂异质结构垂直硅（1-x）Gex/硅纳米管隧道场效应，通过分析不同的器件参数，考虑能带图、电子、空穴浓度、电势和电场，对其性能进行了扫描。与纳米线 TFET 相比，该器件的面积和隧道速率更优越，离子/离子交换比为 1.56∗1013，关断电流更低，约为∼10-18A/μm。该器件的漏极电流 (IDS) 为 2.39∗105A/μm。所建议的器件结构采用 Si(1-x)Gex/Si 结构，具有更强的特性，如改善了阈下斜率的陡度、离子/离子交换比、漏极电流和降低了关断电流。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.