Min Seok Kim, Sang Ho Lee, Jin Park, So Ra Jeon, Seung Ji Bae, Jeong Woo Hong, Jaewon Jang, Jin-Hyuk Bae, Young Jun Yoon, In Man Kang
{"title":"Statistical Analysis of Increased Immunity to Poly-Si Grain Boundaries in Nanosheet CMOS Logic Inverter Through Sheet Stacking","authors":"Min Seok Kim, Sang Ho Lee, Jin Park, So Ra Jeon, Seung Ji Bae, Jeong Woo Hong, Jaewon Jang, Jin-Hyuk Bae, Young Jun Yoon, In Man Kang","doi":"10.1007/s12633-024-03113-6","DOIUrl":null,"url":null,"abstract":"<div><p>Herein, the advantages of sheet stacking in polycrystalline Si (Poly-Si)–based nanosheet MOSFETs and CMOS inverters were statistically analyzed through technology computer-aided design simulations. Poly-Si is used as the channel material to make the high-density three-dimensional structure in a simple process. We studied the transfer characteristics of single-layer nanosheet (SN) MOSFETs and 3-layer multi-bridge nanosheet (MN) MOSFETs depending on the location and the number of grain boundaries (GBs). Further, the DC/switching performance of SN CMOS and MN CMOS inverters was analyzed based on the location and number of GBs. The multilayer stacked structure not only increased the average on state current and switching speed but also reduced the dispersion of characteristics and performance. In addition, multilayer stacked structure increased the yield based on the 3 sigma-level. Therefore, the stacked MN structure is suitable for implementation in MOSFETs and CMOS inverters with high performance and reliability against fluctuations caused by poly-Si GBs.</p></div>","PeriodicalId":776,"journal":{"name":"Silicon","volume":"16 16","pages":"5855 - 5864"},"PeriodicalIF":2.8000,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Silicon","FirstCategoryId":"88","ListUrlMain":"https://link.springer.com/article/10.1007/s12633-024-03113-6","RegionNum":3,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"CHEMISTRY, PHYSICAL","Score":null,"Total":0}
引用次数: 0
Abstract
Herein, the advantages of sheet stacking in polycrystalline Si (Poly-Si)–based nanosheet MOSFETs and CMOS inverters were statistically analyzed through technology computer-aided design simulations. Poly-Si is used as the channel material to make the high-density three-dimensional structure in a simple process. We studied the transfer characteristics of single-layer nanosheet (SN) MOSFETs and 3-layer multi-bridge nanosheet (MN) MOSFETs depending on the location and the number of grain boundaries (GBs). Further, the DC/switching performance of SN CMOS and MN CMOS inverters was analyzed based on the location and number of GBs. The multilayer stacked structure not only increased the average on state current and switching speed but also reduced the dispersion of characteristics and performance. In addition, multilayer stacked structure increased the yield based on the 3 sigma-level. Therefore, the stacked MN structure is suitable for implementation in MOSFETs and CMOS inverters with high performance and reliability against fluctuations caused by poly-Si GBs.
期刊介绍:
The journal Silicon is intended to serve all those involved in studying the role of silicon as an enabling element in materials science. There are no restrictions on disciplinary boundaries provided the focus is on silicon-based materials or adds significantly to the understanding of such materials. Accordingly, such contributions are welcome in the areas of inorganic and organic chemistry, physics, biology, engineering, nanoscience, environmental science, electronics and optoelectronics, and modeling and theory. Relevant silicon-based materials include, but are not limited to, semiconductors, polymers, composites, ceramics, glasses, coatings, resins, composites, small molecules, and thin films.