Ultra-Low Dark Count Rate SPAD Fully Integrated in a 180 nm High-Voltage CMOS Process

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Borna Požar;Ivan Berdalović;Tihomir Knežević;Tomislav Suligoj
{"title":"Ultra-Low Dark Count Rate SPAD Fully Integrated in a 180 nm High-Voltage CMOS Process","authors":"Borna Požar;Ivan Berdalović;Tihomir Knežević;Tomislav Suligoj","doi":"10.1109/LPT.2024.3457009","DOIUrl":null,"url":null,"abstract":"A novel structure of a single-photon avalanche diode (SPAD) fabricated in a commercial \n<inline-formula> <tex-math>$\\boldsymbol {180}$ </tex-math></inline-formula>\n nm high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) process is presented. Device performance in terms of dark count rate (DCR) and photon detection probability (PDP) is compared to a previously published design fabricated as a reference on the same die. We find that the new structure exhibits a DCR of \n<inline-formula> <tex-math>$\\boldsymbol {0.11}$ </tex-math></inline-formula>\n Hz/\n<inline-formula> <tex-math>$\\boldsymbol {\\mu }$ </tex-math></inline-formula>\nm\n<inline-formula> <tex-math>$\\boldsymbol {^{2}}$ </tex-math></inline-formula>\n at an excess voltage of \n<inline-formula> <tex-math>$\\boldsymbol {5}$ </tex-math></inline-formula>\n V, which is among the lowest ever reported in a foundry CMOS process, and more than \n<inline-formula> <tex-math>$\\boldsymbol {3}$ </tex-math></inline-formula>\n times lower with respect to the reference device. Moreover, the new structure shows a PDP/DCR ratio higher by up to a factor of \n<inline-formula> <tex-math>$\\boldsymbol {4.2}$ </tex-math></inline-formula>\n compared to the reference device. The reasons underlying the differences in DCR and PDP between the two structures are explained using technology computer-aided design (TCAD) simulations. The novel device is demonstrated as promising for the design of low-cost SPAD array imagers, particularly in low-noise applications.","PeriodicalId":13065,"journal":{"name":"IEEE Photonics Technology Letters","volume":null,"pages":null},"PeriodicalIF":2.3000,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Photonics Technology Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10671577/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

A novel structure of a single-photon avalanche diode (SPAD) fabricated in a commercial $\boldsymbol {180}$ nm high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) process is presented. Device performance in terms of dark count rate (DCR) and photon detection probability (PDP) is compared to a previously published design fabricated as a reference on the same die. We find that the new structure exhibits a DCR of $\boldsymbol {0.11}$ Hz/ $\boldsymbol {\mu }$ m $\boldsymbol {^{2}}$ at an excess voltage of $\boldsymbol {5}$ V, which is among the lowest ever reported in a foundry CMOS process, and more than $\boldsymbol {3}$ times lower with respect to the reference device. Moreover, the new structure shows a PDP/DCR ratio higher by up to a factor of $\boldsymbol {4.2}$ compared to the reference device. The reasons underlying the differences in DCR and PDP between the two structures are explained using technology computer-aided design (TCAD) simulations. The novel device is demonstrated as promising for the design of low-cost SPAD array imagers, particularly in low-noise applications.
在 180 纳米高压 CMOS 工艺中完全集成超低暗计数率 SPAD
本文介绍了一种新型结构的单光子雪崩二极管(SPAD),它是在商用 $/boldsymbol {180}$ 纳米高压(HV)互补金属氧化物半导体(CMOS)工艺中制造的。器件在暗计数率 (DCR) 和光子检测概率 (PDP) 方面的性能与之前发布的在相同芯片上作为参考制造的设计进行了比较。我们发现,在过剩电压为 $\boldsymbol {5}$ V 时,新结构的 DCR 为 $\boldsymbol {0.11}$ Hz/ $\boldsymbol {/mu }$ m $\boldsymbol {^{2}}$,是代工 CMOS 工艺中报告的最低值之一,比参考器件低 $\boldsymbol {3}$ 多倍。此外,与参考器件相比,新结构的 PDP/DCR 比高达 $\boldsymbol {4.2}$。利用技术计算机辅助设计(TCAD)模拟解释了两种结构的 DCR 和 PDP 存在差异的原因。研究表明,这种新型器件有望用于低成本 SPAD 阵列成像器的设计,特别是在低噪声应用中。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
IEEE Photonics Technology Letters
IEEE Photonics Technology Letters 工程技术-工程:电子与电气
CiteScore
5.00
自引率
3.80%
发文量
404
审稿时长
2.0 months
期刊介绍: IEEE Photonics Technology Letters addresses all aspects of the IEEE Photonics Society Constitutional Field of Interest with emphasis on photonic/lightwave components and applications, laser physics and systems and laser/electro-optics technology. Examples of subject areas for the above areas of concentration are integrated optic and optoelectronic devices, high-power laser arrays (e.g. diode, CO2), free electron lasers, solid, state lasers, laser materials'' interactions and femtosecond laser techniques. The letters journal publishes engineering, applied physics and physics oriented papers. Emphasis is on rapid publication of timely manuscripts. A goal is to provide a focal point of quality engineering-oriented papers in the electro-optics field not found in other rapid-publication journals.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信