TiCoSb Heusler alloy-based magnetic tunnel junction for efficient computing in memory architecture

Abstract

Computing in memory (CiM) architecture enables computation within the memory array, reducing power-intensive data transmission between the processor and memory. The primary goal of this work is to enhance the energy efficiency of CiM architectures that use spintronic devices. Experiments show that the thermal stability (\(\Delta\)) in magnetic tunnel junctions (MTJs) can be optimized to reduce write energy by adjusting the oxide layer thickness. Based on this finding, this work explores a novel spin-orbit torque random-access memory (SOT) cell that yields a 30% increase in energy efficiency compared to conventional SOT. However, reducing the oxide layer thickness below 1.5 nm to tune \(\Delta\) leads to a decrease in the tunnel magnetoresistance (TMR) ratio leading to reliability concerns. The second part of the work proposes to improve TMR by replacing the conventional MgO oxide layer with a TiCoSb Heusler alloy-based layer and utilizing \(\hbox {Co}_{2}\hbox {MnSb}\) as the electrode in the modified cell called \(\Delta\)M-SOT. Theoretical and experimental studies demonstrate that this alternative MTJ design exhibits TMR ratios comparable to values reported in the literature. The performance of magnetic full adder CiM design using the proposed \(\Delta\)M-SOT is compared with designs implemented using CMOS, spin-transfer torque random-access RAM (STT), and conventional SOT. Evaluations show that the \(\Delta\)M-SOT-CiM has a reduction of 66% and 30% in logic and data transfer energy, respectively, compared to conventional SOT-CiM design. Furthermore, the data storage and computation operations in \(\Delta\)M-SOT-CiM are found to be significantly faster compared to both STT- and SOT-CiM design. Overall, this work presents a promising SOT design that effectively bridges the gap between the processor and memory by enabling logical functions within memory, eliminating the need for additional circuits.