HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-29 DOI:10.1109/TVLSI.2024.3445108

Jafar Vafaei;Omid Akbari

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引用次数: 0

Abstract

For critical applications that require a higher level of reliability, the triple modular redundancy (TMR) scheme is usually employed to implement fault-tolerant arithmetic units. However, this method imposes a significant area and power/energy overhead. Also, the majority-based voter in the typical TMR designs is highly sensitive to soft errors and the design diversity of the triplicated module, which may result in an error for a small difference between the output of the TMR modules. However, a wide range of applications deployed in critical systems are inherently error-resilient, that is, they can tolerate some inexact results at their output while having a given level of reliability. In this article, we propose a high precision redundancy multiplier (HPR-Mul) that relies on the principles of approximate computing to achieve higher energy efficiency and lower area, as well as resolve the aforementioned challenges of the typical TMR schemes, while retaining the required level of reliability. The HPR-Mul is composed of full precision (FP) and two reduced precision (RP) multipliers, along with a simple voter to determine the output. Unlike the state-of-the-art RP redundancy multipliers (RPR-Muls) that require a complex voter, the voter of the proposed HPR-Mul is designed based on mathematical formulas resulting in a simpler structure. Furthermore, we use the intermediate signals of the FP multiplier as the inputs of the RP multipliers, which significantly enhance the accuracy of the HPR-Mul. The efficiency of the proposed HPR-Mul is evaluated in a 15-nm FinFET technology, where the results show up to 70% and 69% lower power consumption and area, respectively, compared to the typical TMR-based multipliers. Also, the HPR-Mul outperforms the state-of-the-art RPR-Mul by achieving up to 84% higher soft error tolerance. Moreover, by employing the HPR-Mul in different image processing applications, up to 13% higher output image quality is achieved in comparison with the state-of-the-art RPR multipliers.

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HPR-Mul：通过近似计算实现面积和能效的高精度冗余乘法器

对于需要更高可靠性的关键应用，通常采用三重模块冗余（TMR）方案来实现容错算术单元。然而，这种方法会带来巨大的面积和功耗/能耗开销。此外，典型的 TMR 设计中基于多数的表决器对软错误和三重模块的设计多样性高度敏感，这可能导致 TMR 模块输出之间的微小差异就会产生错误。然而，部署在关键系统中的各种应用本身都具有抗错能力，也就是说，它们可以在具有一定可靠性水平的同时，容忍输出端出现一些不精确的结果。在本文中，我们提出了一种高精度冗余乘法器（HPR-Mul），它依靠近似计算原理实现了更高的能效和更小的面积，并解决了上述典型 TMR 方案所面临的挑战，同时保持了所需的可靠性水平。HPR-Mul 由全精度（FP）乘法器和两个降低精度（RP）乘法器组成，并通过一个简单的投票器确定输出。与需要复杂投票器的最先进 RP 冗余乘法器（RPR-Muls）不同，拟议的 HPR-Mul 的投票器是根据数学公式设计的，因此结构更简单。此外，我们使用 FP 倍增器的中间信号作为 RP 倍增器的输入，这大大提高了 HPR-Mul 的精度。我们在 15 纳米 FinFET 技术中对所提出的 HPR-Mul 的效率进行了评估，结果显示，与典型的基于 TMR 的乘法器相比，功耗和面积分别降低了 70% 和 69%。此外，HPR-Mul 的软容错能力比最先进的 RPR-Mul 高出 84%。此外，在不同的图像处理应用中使用 HPR-Mul 时，输出图像质量比最先进的 RPR 乘法器高出 13%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.