A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI:10.1109/TVLSI.2024.3447740

Yang Zhou;Wenjie Wang;Longbin Zhu;Zhengtao Zhu;Risheng Su;Jianan Zheng;Siyuan Xie;Jihong Li;Fanyi Meng;Zhijun Zhou;Keping Wang

引用次数: 0

Abstract

This brief proposes a parallel multiresidual (PMR) integrator to enhance the noise-shaping (NS) effect for successive approximation register (SAR) analog-to-digital converter (ADC). The PMR employs passive integrators in parallel to simultaneously integrate the average result of the multiple sequential residual voltages. The proposed PMR technique provides an alternative scheme to enhance the NS rather than increasing the order of the integrator to suppress the instability and power. A prototype 7-bit second-order NS-SAR ADC is designed and simulated in a 130-nm CMOS process. PMR increases the effective number of bits (ENOBs) to 10.6 bit, which enhances the NS effect of 3.6 bit. It achieves a peak signal-to-noise and distortion ratio (SNDR) of 65.84 dB over a bandwidth of 1.3 kHz at the oversampling ratio (OSR) of 16.

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带并行多冗余积分器的二阶噪声整形 SAR ADC

本文提出了一种并行多残差（PMR）积分器，以增强逐次逼近寄存器（SAR）模数转换器（ADC）的噪声整形（NS）效果。PMR 采用并联无源积分器，同时对多个连续残余电压的平均结果进行积分。所提出的 PMR 技术提供了另一种增强 NS 的方案，而不是增加积分器的阶数来抑制不稳定性和功耗。在 130 纳米 CMOS 工艺中设计并模拟了一个 7 位二阶 NS-SAR ADC 原型。PMR 将有效位数 (ENOB) 提高到 10.6 位，从而增强了 3.6 位的 NS 效果。在过采样率（OSR）为 16 的 1.3 kHz 带宽上，它实现了 65.84 dB 的峰值信噪比和失真比（SNDR）。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.