A 0.05–1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications

Abstract

This work introduces a dual-channel digital-to-time converter (DTC) featuring a broad tuning range, which utilizes a dual delay-locked loop (DLL) architecture to achieve clock or data deskewing and precise timing adjustment effectively. The coarse- and fine-tuning mechanisms are operated in precise closed-loop schemes to lessen the effects of the ambient variations. The replica fine voltage-controlled delay line can provide subgate resolution and instantaneous switching capability. Then, the replica coarse voltage-controlled delay line can provide a wide dynamic delay range. The proposed DTC can generate variable delays for an arbitrary pseudorandom data rate of up to 3 Gb/s and is insensitive to process and temperature variation. The test chip, fabricated in a 55-nm CMOS process, operates from 0.05 to 1.5 GHz and achieves a timing resolution of 9.77 ps, a power consumption of 12 mW, and an area of 0.76 mm2. The measured maximum integral nonlinearity (INL) is 2.20 LSB in an extended delay mode. In the dual delay mode, the maximum INL of channels 0 and 1 is 1.60 and −1.08 LSB, respectively.