{"title":"Ultra-Low-Power High PSRR Sub-1 V Voltage Reference Circuit in 22 nm FDSOI CMOS","authors":"Adilet Dossanov;Christian Ziegler;Vadim Issakov","doi":"10.1109/TCSII.2024.3443459","DOIUrl":null,"url":null,"abstract":"This brief presents an ultra-low-power sub-1V voltage reference circuit using a self-cascode technique to improve power supply rejection ratio (PSRR) for battery-powered applications. The proposed voltage reference circuit has been fabricated in 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology, and it occupies an active area of 0.0104\n<inline-formula> <tex-math>$\\text {mm}^{{2}}$ </tex-math></inline-formula>\n. The measured average output voltage \n<inline-formula> <tex-math>$\\text {V}_{\\text {REF}}$ </tex-math></inline-formula>\n from 12 samples at room temperature is 598 mV with a standard deviation of 0.37%. The \n<inline-formula> <tex-math>$\\text {V}_{\\text {REF}}$ </tex-math></inline-formula>\n shows measured average temperature coefficient \n<inline-formula> <tex-math>$\\text {TC}_{\\text {avg}}$ </tex-math></inline-formula>\n of 61\n<inline-formula> <tex-math>$\\text {ppm/}^{\\circ }\\text {C}$ </tex-math></inline-formula>\n over the temperature range of −40°C to 120°C, line sensitivity of 0.12%/V from 1.2V to 1.8V supply voltages, and measured PSRR of 66 dB at 10 Hz. A total power consumption is 45.6nW from a 1.2V supply voltage.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4643-4647"},"PeriodicalIF":4.0000,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10636750/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This brief presents an ultra-low-power sub-1V voltage reference circuit using a self-cascode technique to improve power supply rejection ratio (PSRR) for battery-powered applications. The proposed voltage reference circuit has been fabricated in 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology, and it occupies an active area of 0.0104
$\text {mm}^{{2}}$
. The measured average output voltage
$\text {V}_{\text {REF}}$
from 12 samples at room temperature is 598 mV with a standard deviation of 0.37%. The
$\text {V}_{\text {REF}}$
shows measured average temperature coefficient
$\text {TC}_{\text {avg}}$
of 61
$\text {ppm/}^{\circ }\text {C}$
over the temperature range of −40°C to 120°C, line sensitivity of 0.12%/V from 1.2V to 1.8V supply voltages, and measured PSRR of 66 dB at 10 Hz. A total power consumption is 45.6nW from a 1.2V supply voltage.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.