A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC

IF 4 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-27 DOI:10.1109/TCSII.2024.3450695

Jaewon Lee;Seoyoung Jang;Donggeon Kim;Yujin Choi;Jong-Hyeok Yoon;Matthias Braendli;Thomas Morf;Marcel Kossel;Pier-Andrea Francese;Gain Kim

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引用次数: 0

Abstract

This brief presents a discrete multi-tone (DMT) wireline transceiver (TRX) datapath and introduces the RFSoC-based real-time hardware platform to quickly sweep the optimum bit and power loading profile constrained by the peak-to-average-power ratio (PAPR). The datapath is implemented based on 32-parallel multi-path delay feedback (MDF) fast Fourier transform (FFT)/inverse FFT (IFFT) processors to save resources, integrating with the sign-sign least mean square (SS-LMS) engine. The loading is computed for the channel signal-to-noise ratio (SNR) and PAPR. The platform consists of 2.048 GS/s data converters, the DMT datapath implemented on programmable logic (PL) running at 64 MHz, and the channel board. This system enables a quick bit-error-rate (BER) test at an order of 1.0E-9, accelerating the finding of optimal loading with realistic hardware effects and random clipping events. Experimental results show that the data rate could reach a maximum of 6.82 Gb/s at a BER of 5.7E-4 and a minimum BER of 3.7E-7 for a target data rate of 4.81 Gb/s with a channel exhibiting 16.3 dB insertion loss (IL) at Nyquist.

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RFSoC 上具有片上 Sign-Sign LMS 自适应和加载配置文件优化功能的离散多音有线收发器数据路径

本简介介绍了一种离散多音（DMT）有线收发器（TRX）数据路径，并介绍了基于 RFSoC 的实时硬件平台，用于快速扫描受峰值-平均功率比（PAPR）限制的最佳位和功率负载曲线。数据通路基于 32 个并行多路径延迟反馈（MDF）快速傅立叶变换（FFT）/反向 FFT（IFFT）处理器实现，以节省资源，并与符号最小均方（SS-LMS）引擎集成。负载是根据信道信噪比（SNR）和 PAPR 计算得出的。该平台由 2.048 GS/s 数据转换器、在运行频率为 64 MHz 的可编程逻辑 (PL) 上实现的 DMT 数据路径和信道板组成。该系统能以 1.0E-9 的数量级进行快速误码率 (BER) 测试，从而加快找到具有真实硬件效应和随机削波事件的最佳负载。实验结果表明，在误码率为 5.7E-4 的情况下，数据传输速率最高可达 6.82 Gb/s；在奈奎斯特插入损耗（IL）为 16.3 dB 的情况下，目标数据传输速率为 4.81 Gb/s，误码率最低为 3.7E-7。

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来源期刊

IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程：电子与电气

CiteScore

7.90

自引率

20.50%

发文量

883

审稿时长

3.0 months

期刊介绍： TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.