A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption

Abstract

To accelerate RNS-CKKS, little attention is paid to the acceleration of the operations on the edge-client. However, the devices used by the edge-client are often low-end and have limited resources and computing power, so the performance of RNS-CKKS encoding, decoding, encryption and decryption also needs to be improved. Consequently, we propose a compact and efficient hardware accelerator architecture named CAEA for these operations. In order to improve the compactness of CAEA, a reconfigurable butterfly unit is proposed, which considers both complex number arithmetic and integer modular arithmetic, so that FFT/IFFT and NTT/INTT can be executed on unified hardware processing elements without additional resource and waste. Moreover, in order to improve the computational efficiency, we also improved the dataflow of encoding, decoding, encryption, and decryption on CAEA to reduce the number of required operations and latency. CAEA is synthesized based on SMIC 40nm technology, and is also implemented on Xilinx Kintex-7 and Zynq UltraScale+ FPGA. Compared with the prior related works, in terms of performance, CAEA can achieve $2.01\times $ speedup for encoding and decoding, $1.13\times \sim ~87.86\times $ speedup for encryption, and $3.03\times \sim ~69.64\times $ speedup for decryption. Compared with the state-of-the-art work, CAEA can achieve $1.06\times \sim ~4.96\times $ improvement in terms of area efficiency.