Containerized In-Storage Processing Model and Hardware Acceleration for Fully-Flexible Computational SSDs

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-06-27 DOI:10.1109/lca.2023.3289828

Donghyun Gouk, Miryeong Kwon, Hanyeoreum Bae, Myoungsoo Jung

引用次数: 0

Abstract

In-storage processing (ISP) efficiently examines large datasets but faces performance and security challenges. We introduce DockerSSD, a flexible ISP model that runs various applications near flash without modification. It employs lightweight OS-level virtualization in modern SSDs for faster ISP and better storage intelligence with a high flexiblity. DockerSSD reuses existing Docker container images for real-time data processing without altering the storage interface or runtime. Our design includes a new communication method and virtual firmware, alongside automated container-related network and I/O handling hardware. DockerSSD achieves a 2× speed improvement and reduces system-level power by 35.7%, on average.

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用于全灵活计算固态硬盘的容器化存储内处理模型和硬件加速

存储内处理（ISP）可有效检查大型数据集，但面临着性能和安全方面的挑战。我们引入了 DockerSSD，这是一种灵活的 ISP 模式，可在闪存附近运行各种应用，无需修改。它在现代固态硬盘中采用了轻量级操作系统级虚拟化技术，以实现更快的 ISP 和更高灵活性的存储智能。DockerSSD 可重复使用现有的 Docker 容器镜像进行实时数据处理，而无需更改存储接口或运行时。我们的设计包括新的通信方法和虚拟固件，以及与容器相关的自动化网络和 I/O 处理硬件。DockerSSD 的速度提高了 2 倍，系统级功耗平均降低了 35.7%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.