A Node-Based Polar List Decoder With Frame Interleaving and Ensemble Decoding Support

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Yuqing Ren;Leyu Zhang;Ludovic Damien Blanc;Yifei Shen;Xinwei Li;Alexios Balatsoukas-Stimming;Chuan Zhang;Andreas Burg
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引用次数: 0

Abstract

Node-based successive cancellation list (SCL) decoding has received considerable attention in wireless communications for its significant reduction in decoding latency, particularly with 5G New Radio (NR) polar codes. However, the existing node-based SCL decoders are constrained by sequential processing, leading to complicated and data-dependent computational units that introduce unavoidable stalls, reducing hardware efficiency. In this paper, we present a frame-interleaving hardware architecture for a generalized node-based SCL decoder. By efficiently reusing otherwise idle computational units, two independent frames can be decoded simultaneously, resulting in a significant throughput gain. Based on this new architecture, we further exploit graph ensembles to diversify the decoding space, thus enhancing the error-correcting performance with a limited list size. Two dynamic strategies are proposed to eliminate the residual stalls in the decoding schedule, which eventually results in nearly $2 \times $ throughput compared to the state-of-the-art baseline node-based SCL decoder. To impart the decoder rate flexibility, we develop a novel online instruction generator to identify the generalized nodes and produce instructions on-the-fly. The corresponding 28nm FD-SOI ASIC SCL decoder with a list size of 8 has a core area of 1.28 mm2 and operates at 692 MHz. It is compatible with all 5G NR polar codes and achieves a throughput of 3.34 Gbps and an area efficiency of 2.62 Gbps/mm2 for uplink (1024, 512) codes, which is $1.41 \times $ and $1.69 \times $ better than the state-of-the-art node-based SCL decoders.
支持帧交错和集合解码的基于节点的极性列表解码器
基于节点的连续消隐列表(SCL)解码因其显著降低解码延迟而在无线通信领域受到广泛关注,特别是在 5G 新无线电(NR)极性编码方面。然而,现有的基于节点的 SCL 解码器受限于顺序处理,导致计算单元复杂且依赖数据,从而引入了不可避免的停滞,降低了硬件效率。在本文中,我们为基于节点的通用 SCL 解码器提出了一种帧交错硬件架构。通过有效重用原本闲置的计算单元,可以同时解码两个独立的帧,从而显著提高吞吐量。在这种新架构的基础上,我们进一步利用图集合来分散解码空间,从而在有限的列表大小下提高纠错性能。我们提出了两种动态策略来消除解码计划中的残余停滞,最终与最先进的基于节点的基线 SCL 解码器相比,吞吐量提高了近 2 美元。为了赋予解码器速率灵活性,我们开发了一种新型在线指令生成器,用于识别广义节点并即时生成指令。相应的 28nm FD-SOI ASIC SCL 解码器的列表大小为 8,内核面积为 1.28 mm2,工作频率为 692 MHz。它兼容所有5G NR极性编码,上行链路(1024,512)编码的吞吐量达到3.34 Gbps,面积效率为2.62 Gbps/mm2,比最先进的基于节点的SCL解码器分别高出1.41倍和1.69倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
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