A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination

IF 5.2 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-12 DOI:10.1109/TCSI.2024.3422082

Wenzheng He;Zikuo Lu;Xin Liu;Ziwei Xu;Jingshuo Zhang;Chen Yang;Li Geng

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引用次数: 0

Abstract

The visual SLAM (vSLAM) algorithm is becoming a research hotspot in recent years because of its low cost and low delay. Due to the advantage of fitting irregular data input, random sample consensus (RANSAC) has become a commonly used method in vSLAM to eliminate mismatched feature point pairs in adjacent frames. However, the huge number of iterations and computational complexity of the algorithm make the hardware implementation and integration of the entire system challenging. This paper pioneeringly proposes an efficient hardware acceleration design with homography matrix as RANSAC hypothesis model, which achieves high speed and high precision. Through optimizing the direct linear transformation (DLT) method, the delay and resource consumption are reduced. The design is implemented on FPGA. Through the verification of Xilinx Zynq 7100 platform, the processing frame rate on EuRoc dataset is 709 fps, reaching an average speed up of

$263.2\times $

against ARM CPU, and a speed up of

$1.2\sim 50.0\times $

compared with the advanced implementations in RANSAC part, which fully meets the real-time requirements. In addition, the root-mean-square error (RMSE) based on an open-source SLAM system (ICE-BA) on the EuRoc dataset reached 0.105 m, achieving an improvement of 15.6% in precision compared to the original ICE-BA system.

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用于视觉 SLAM 的 RANSAC 算法的实时和高精度硬件实现，实现错配特征点对消除

视觉 SLAM（vSLAM）算法因其低成本、低延迟而成为近年来的研究热点。由于具有拟合不规则数据输入的优势，随机抽样共识（RANSAC）已成为 vSLAM 中消除相邻帧中不匹配特征点对的常用方法。然而，该算法迭代次数多、计算复杂，给整个系统的硬件实现和集成带来了挑战。本文开创性地提出了一种以同构矩阵作为 RANSAC 假设模型的高效硬件加速设计，实现了高速度和高精度。通过优化直接线性变换（DLT）方法，减少了延迟和资源消耗。该设计在 FPGA 上实现。通过Xilinx Zynq 7100平台的验证，在EuRoc数据集上的处理帧速率为709帧/秒，与ARM CPU相比平均提速263.2倍，与RANSAC部分的先进实现相比提速1.2美元/sim 50.0倍，完全满足实时性要求。此外，在EuRoc数据集上，基于开源SLAM系统（ICE-BA）的均方根误差（RMSE）达到了0.105 m，与原始ICE-BA系统相比，精度提高了15.6%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程：电子与电气

CiteScore

9.80

自引率

11.80%

发文量

441

审稿时长

2 months

期刊介绍： TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.