A 3D-stack DRAM-based PNM architecture design

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-09-02 DOI:10.1016/j.vlsi.2024.102266

Qiang Zhou , Bing Wang , XinTing Xiao

引用次数: 0

Abstract

The article examines methods for integrating 3D-stacked DRAM with AI logic chips, in order to overcome the memory bandwidth challenges faced in the AI inference of transformer models. The findings indicate that this approach can yield a 9x to 3x reduction in power consumption while maintaining similar performance levels, or alternatively, an 8x improvement in performance with comparable power consumption.

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基于 3D 堆栈 DRAM 的 PNM 架构设计

文章研究了将三维堆叠 DRAM 与人工智能逻辑芯片集成的方法，以克服变压器模型的人工智能推理所面临的内存带宽挑战。研究结果表明，这种方法可以在保持类似性能水平的同时将功耗降低 9 到 3 倍，或者在功耗相当的情况下将性能提高 8 倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.