An Efficient and Fast Area Optimization Approach for Mixed Polarity Reed-Muller Logic Circuits

Abstract

Area has become one of the main bottlenecks restricting the development of integrated circuits. The area optimization approaches of existing XNOR/OR-based mixed polarity Reed-Muller (MPRM) circuits have poor optimization effect and efficiency. Given that the area optimization of MPRM logic circuits is a combinatorial optimization problem, we propose a whole annealing adaptive bacterial foraging algorithm (WAA-BFA), which includes individual evolution based on Markov chain and Metropolis acceptance criteria, and individual mutation based on adaptive probability. To address the issue of low conversion efficiency in existing polarity conversion approaches, we introduce a fast polarity conversion algorithm (FPCA). Moreover, we present an MPRM circuits area optimization approach that uses the FPCA and WAA-BFA to search for the best polarity corresponding to the minimum circuits area. Experimental results demonstrate that the proposed MPRM circuits area optimization approach is effective and can be used as a promising EDA tool.