Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-09-07 DOI:10.1016/j.mejo.2024.106410

Jing Chen, Jiajun Guo, Qing Yao, Kemeng Yang, Jun Zhang, Jiafei Yao, Yufeng Guo

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引用次数: 0

Abstract

The introduction of the step thickness drift region (ST) technique has increased the design complexity of silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS). This paper proposes a physics-inspired automatic optimization method for the ST structure of SOI LDMOS using constrained simulated annealing algorithm. Since breakdown voltage (BV) and specific on-resistance (R_on,sp) need to be optimized simultaneously, an optimization function based on Baliga's Figure of Merit (BFOM) is introduced. Besides, constraints are introduced to ensure that BV is greater than the initial BV and R_on,sp is less than the initial R_on,sp. Results demonstrate that the BFOM values increase by an average of 134.9 %, 163.6 %, and 113.8 % when the breakdown occurs at the N⁺N junction, PN junction, and in-the-body after optimizing the ST structure, respectively. Besides, introducing constraints during the automatic design process allows for the simultaneous optimization of both the BV and R_on,sp. Furthermore, the proposed method is also efficient, with 86 % of the optimization design processes completed within 18 seconds.

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利用物理学启发的约束模拟退火算法自动设计 SOI LDMOS 的阶跃厚度漂移区

阶梯厚度漂移区（ST）技术的引入增加了硅绝缘体（SOI）横向双扩散金属氧化物半导体（LDMOS）的设计复杂性。本文提出了一种受物理学启发的自动优化方法，利用约束模拟退火算法对 SOI LDMOS 的 ST 结构进行优化。由于击穿电压（BV）和比导通电阻（Ron,sp）需要同时优化，因此引入了基于巴利加功绩图（BFOM）的优化函数。此外，还引入了一些约束条件，以确保 BV 大于初始 BV，Ron,sp 小于初始 Ron,sp。结果表明，优化 ST 结构后，当击穿发生在 N+N 结、PN 结和体内时，BFOM 值平均分别增加了 134.9%、163.6% 和 113.8%。此外，在自动设计过程中引入约束条件可以同时优化 BV 和 Ron,sp。此外，所提出的方法还很高效，86% 的优化设计过程在 18 秒内完成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.