Improvement of digital, analog/RF and linearity performances of charge plasma based junctionless FinFET through spacer layer engineering

Abstract

We investigate the digital, analog/RF, and linearity performance of four CP FinFETs distinguished by spacer layers: (i) single low-k spacer on both sides of the gate (D₁), (ii) single high-k spacer on both sides of the gate (D₂), (iii) a combination of high-k spacer and air on the source side and high-k spacer on the drain side (D₃), and (iv) a combination of high-k spacer and air symmetrically placed on both sides of the gate (D₄) at 10 nm technology node. Our results highlight the superior digital performance of the D₄ device, demonstrating significant enhancements in various analog/RF figures of merit (FOMs) including transconductance, transconductance efficiency, unity gain cut-off frequency (F_T), and gain bandwidth product (GBP). Notably, the D₄ device exhibits a remarkable 256 % improvement in F_T and a substantial 456.13 % enhancement in GBP compared to D₁. Additionally, we analyze linearity and intermodulation distortion performance, suggesting the D₄ device as the optimal architecture for high-performance digital and analog/RF applications.