Efficient O-type mapping and routing of large-scale neural networks to torus-based ONoCs

Abstract

The rapid development of artificial intelligence has accelerated the arrival of the era of large models. Artificial-neural-network-based large models typically have millions to billions of parameters, and their training and reasoning processes put strict requirements on hardware, especially at the chip level, in terms of interconnection bandwidth, processing speed, latency, etc. The optical network-on-chip (ONoC) is a new interconnection technology that connects IP cores through a network of optical waveguides. Due to its incomparable advantages such as low loss, high throughput, and low delay, this communication mode has gradually become the key technology to improve the efficiency of large models. At present, the ONoC has been used to reduce the interconnection complexity of neural network accelerators, where neural network models are reshaped to map into the process elements of the ONoC and communicate at high speed on chip. In this paper, we first propose a torus-based O-type mapping strategy to realize efficient mapping of neuron groups to the chip. Additionally, an array congestion information-based low-congestion arbitrator is designed and then a multi-path low-congestion routing algorithm named TMLA is presented to alleviate array congestion and disperse the routing pressure of each path. Results demonstrate that the proposed mapping and routing scheme can reduce the average network delay without additional loss when the injection rate is relatively large, which provides a valuable reference for the research of neural network acceleration.