Expanding the dose window of step-etched space-modulated JTE for ultrahigh voltage 4H-SiC devices

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-08-25 DOI:10.1016/j.mejo.2024.106387

Lixin Geng, Ruifeng Yue, Yan Wang

引用次数: 0

Abstract

A step-etched space-modulated junction termination extension (SE-SM-JTE) is proposed for ultrahigh voltage (≥10 kV) 4H-SiC devices in this work. The proposed structure creates a stepped effective JTE dose profile by introducing the step etching into space-modulated JTE (SM-JTE), which shows great merits in the compromises of the JTE dose window, termination efficiency, termination area, and the complexity of the fabrication process. According to the TCAD simulation results, the SE-SM-JTE with a length of 300 μm (3 times the drift layer thickness) obtains a wide implantation dose window of ±47 % above 12 kV, achieving a wide tolerance to JTE dose and surface fixed charge. The maximum breakdown voltage (BV) of the proposed SE-SM-JTE is 13.8 kV, exhibiting a termination efficiency of 92 %. Moreover, the proposed JTE structure requires only a single ion implantation and subsequent two etchings, which facilitates the fabrication feasibility in ultrahigh voltage 4H-SiC devices.

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为超高电压 4H-SiC 器件扩展阶跃蚀刻空间调制 JTE 的剂量窗口

本研究为超高电压（≥10 kV）4H-SiC 器件提出了一种阶跃蚀刻空间调制结端接扩展（SE-SM-JTE）。通过在空间调制 JTE（SM-JTE）中引入阶跃蚀刻，所提出的结构创建了一个阶跃的有效 JTE 剂量曲线，在 JTE 剂量窗口、端接效率、端接面积和制造工艺复杂性的折衷方面显示出巨大优势。根据 TCAD 仿真结果，长度为 300 μm（漂移层厚度的 3 倍）的 SE-SM-JTE 在 12 kV 以上可获得 ±47 % 的宽植入剂量窗口，实现了对 JTE 剂量和表面固定电荷的宽容差。拟议的 SE-SM-JTE 的最大击穿电压 (BV) 为 13.8 kV，端接效率高达 92%。此外，所提出的 JTE 结构只需一次离子注入和随后的两次蚀刻，这有助于在超高压 4H-SiC 器件中实现制造可行性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.