Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-08-08 DOI:10.1016/j.mejo.2024.106365

Bo Liu , He Yang , Xiangjun Wang , Ruizhi Xiang , Jun Wang , Liwen Zhang

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引用次数: 0

Abstract

A power-efficient, wide-band, programmable pseudo-differential ring-oscillator charge-pump phase-locked loop (CP-PLL) is proposed. The ring-VCO, characterized by its low power consumption and broadband, is achieved based on a feedforward pseudo-differential configuration. The linearity of ring-VCO is improved by using the source negative feedback topology. Through the rail-to-rail operatingamplifier clamping current source, the current matching accuracy is improved to realize a high-performance CP circuit. The results show that the output frequency range of the phase-locked loop is 0.6–6 GHz at a 1.2 V supply voltage, and the power consumption is 1.372 mW at 5 GHz with a lock-up time of 1.72 μs and RMS jitter of 9.3 ps. The power consumption is as low as 0.643 mW at 2.5 GHz and 1.067 mW at 4 GHz, and the final layout area is 0.00716 mm². The implemented CP-PLL can be used effectively in wireless RF communication system of NB-IoT and intelligent edge computing scenario.

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高能效宽带可编程伪差分环振荡器 CP-PLL

本文提出了一种高能效、宽频带、可编程伪差分环形振荡器电荷泵锁相环（CP-PLL）。该环形振荡器基于前馈伪差分配置，具有低功耗和宽带的特点。通过使用源负反馈拓扑结构，提高了环形 VCO 的线性度。通过轨至轨工作放大器箝位电流源，提高了电流匹配精度，从而实现了高性能的 CP 电路。结果表明，在 1.2 V 电源电压下，锁相环的输出频率范围为 0.6-6 GHz，5 GHz 时的功耗为 1.372 mW，锁定时间为 1.72 μs，有效值抖动为 9.3 ps。在 2.5 GHz 和 4 GHz 时，功耗分别低至 0.643 mW 和 1.067 mW，最终布局面积为 0.00716 mm2。所实现的 CP-PLL 可有效用于 NB-IoT 无线射频通信系统和智能边缘计算场景。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.