A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-07-31 DOI:10.1016/j.mejo.2024.106353

Guolong Fu , Yanbo Zhang , Yan Wang , Zhiyu Zhao , Shubin Liu , Zhangming Zhu

引用次数: 0

Abstract

This paper presents a 4th-order interstage gain error shaping (GES) technique in pipeline successive approximation register (SAR) analog-to-digital converters (ADCs), which can substantially suppress the in-band quantization leakage error induced by the gain error. It is realized by simply arranging a low-order cascaded-integrator feed-forward (CIFF) structure in the first stage. In addition, the comparator noise and quantization error can be shaped together with the gain error in the proposed architecture. Verified by simulation in a 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.8 dB over 25-MHz bandwidth (BW) with oversampling ratio (OSR) of 8. Within a gain error range of −33 % to +33 %, the SNDR of the ADC deviates less than 3 dB. Under a 1 V supply voltage, the ADC consumes 3.75 mW and exhibits a Scherier figure of merit (FoMs) of 176 dB.

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具有阶次增强增益误差整形功能的二阶噪声整形 SAR 辅助流水线 ADC

本文介绍了流水线逐次逼近寄存器（SAR）模数转换器（ADC）中的四阶级间增益误差整形（GES）技术，该技术可大幅抑制增益误差引起的带内量化泄漏误差。它是通过在第一级简单布置一个低阶级联积分器前馈（CIFF）结构来实现的。此外，比较器噪声和量化误差可与拟议架构中的增益误差一起形成。通过在 28-nm CMOS 工艺中进行仿真验证，原型在 25-MHz 带宽（BW）和 8 的过采样率（OSR）条件下实现了 77.8 dB 的信噪比和失真比（SNDR）。在增益误差 -33 % 至 +33 % 的范围内，ADC 的 SNDR 偏差小于 3 dB。在 1 V 电源电压下，模数转换器的功耗为 3.75 mW，Scherier 优点值 (FoMs) 为 176 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.