Self-clamped P-shield 4H-SiC trench MOSFET for low turn-off loss and suppress switching oscillation

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-08-02 DOI:10.1016/j.mejo.2024.106307

Lijuan Wu, Guanglin Yang, Deqiang Yang, Zigui Tu, Jie Yuan, Dongsheng Zhao, Mengjiao Liu, Jiahui Liang

{"title":"Self-clamped P-shield 4H-SiC trench MOSFET for low turn-off loss and suppress switching oscillation","authors":"Lijuan Wu, Guanglin Yang, Deqiang Yang, Zigui Tu, Jie Yuan, Dongsheng Zhao, Mengjiao Liu, Jiahui Liang","doi":"10.1016/j.mejo.2024.106307","DOIUrl":null,"url":null,"abstract":"<div>A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When VDS is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (CGD). As VDS increases, the LP region is gradually depleted, causing the P-shield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(VSurge). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better EOFF-VSurge trade-off.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000110","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When V_DS is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (C_GD). As V_DS increases, the LP region is gradually depleted, causing the P-shield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(V_Surge). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better E_OFF-V_Surge trade-off.

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自夹式 P 屏蔽 4H-SiC 沟槽 MOSFET，可降低关断损耗并抑制开关振荡

本文提出了一种新型 4H-SiC 沟槽 MOSFET，具有自钳位 P 区（SCP-MOS）。通过引入轻 P 型掺杂浓度区（LP）和额外的 NCSL，提高了击穿电压并抑制了开关振荡。P+ 和 NCSL 形成了一个新的电场调制区，可降低栅极底部的电场，从而提高器件的击穿电压。此外，当 VDS 较小时，LP 区域连接 P 屏蔽和 P+ 源区，P 屏蔽被箝位在低电位，从而有效降低了栅极到漏极电容 (CGD)。随着 VDS 的增加，LP 区逐渐耗尽，导致 P 屏蔽区过渡到浮动状态，P 屏蔽区的电位升高。因此，上述特性有助于实现较低的关断损耗和浪涌电压（VSurge）。SCP-MOS 的浪涌电压比 GP-MOS 低 32%，关断损耗比 FP-MOS 低 85%。总体而言，SCP-MOS 可以实现更好的关断-浪涌权衡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.