{"title":"Self-clamped P-shield 4H-SiC trench MOSFET for low turn-off loss and suppress switching oscillation","authors":"Lijuan Wu, Guanglin Yang, Deqiang Yang, Zigui Tu, Jie Yuan, Dongsheng Zhao, Mengjiao Liu, Jiahui Liang","doi":"10.1016/j.mejo.2024.106307","DOIUrl":null,"url":null,"abstract":"<div><p>A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When <em>V</em><sub>DS</sub> is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (<em>C</em><sub>GD</sub>). As <em>V</em><sub>DS</sub> increases, the LP region is gradually depleted, causing the P-shield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(<em>V</em><sub>Surge</sub>). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better <em>E</em><sub>OFF</sub>-<em>V</em><sub>Surge</sub> trade-off.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000110","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When VDS is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (CGD). As VDS increases, the LP region is gradually depleted, causing the P-shield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(VSurge). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better EOFF-VSurge trade-off.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
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