A high speed pipelined radix-16 Booth multiplier architecture for FPGA implementation

Abstract

Since multiplication is a complex and resource-consuming operation, it is very effective on the speed performance of a processor. In this regard, fast multiplication unit design is important in digital system architectures. FPGA hardware, which is efficient for the implementation and rapid prototyping of today’s digital system architectures, is becoming widespread. Therefore, in this study it aimed to design a fast radix-16 Booth multiplier based on the FPGA architecture. Booth multiplier implementation is preferred because it is relatively simple and efficient. The sizes of the multiplexers, which have an impact on the operating period in the encoder part of the proposed multiplier, reduced in the designed architecture by using a simple algorithm. To increase the speed performance of the system, the pipeline technique is used and parallelization is preferred in the tree structure in addition of the partial products. The effects of different multiplexer sizes, bit lengths and pipeline stages on the operating period of the system and other performance metrics examined. Different designs and the results obtained presented. According to the results, the multiplier hardware architectures designed in this study exhibit effective results in terms of speed performance.