Quantized CNN-based efficient hardware architecture for real-time hand gesture recognition

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
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引用次数: 0

Abstract

Nowadays, Convolutional Neural Networks (CNN) have been widely adopted for vision-based hand gesture recognition. Several existing CNN architectures designed for gesture classification perform well with high accuracy but require a high memory footprint and processing when deployed on low-power embedded devices. To address this issue, we present a quantized CNN-based efficient framework for meeting real-life hand gesture recognition challenges. The proposed quantized CNN is designed and implemented using the FINN-based pipelined streaming architecture on an FPGA. Moreover, hardware-based optimizations are used to minimize the resources needed and to achieve fast memory access. Experimental results demonstrate that the developed recognition system achieves an average accuracy of 92% on the numeral database of Indian Sign Language (ISL). Additionally, our optimized design attains an inference latency of 0.85ms for real-time single gesture prediction on the PYNQ Zynq Ultrascale (ZU) FPGA, consuming only 3.63 W of power. The proposed design achieves a better trade-off between hardware resource utilization and speed performance, over previous designs.

基于量化 CNN 的实时手势识别高效硬件架构
如今,基于视觉的手势识别已广泛采用卷积神经网络(CNN)。现有的几种 CNN 架构专为手势分类而设计,具有良好的性能和较高的准确度,但部署在低功耗嵌入式设备上时需要占用较多内存和处理能力。为解决这一问题,我们提出了一种基于量化 CNN 的高效框架,以应对现实生活中的手势识别挑战。所提出的量化 CNN 是在 FPGA 上使用基于 FINN 的流水线架构设计和实现的。此外,还采用了基于硬件的优化技术,以最大限度地减少所需资源并实现快速内存访问。实验结果表明,所开发的识别系统在印度手语(ISL)数字数据库上的平均准确率达到 92%。此外,我们的优化设计在PYNQ Zynq Ultrascale(ZU)FPGA上进行实时单手势预测时,推理延迟为0.85毫秒,功耗仅为3.63瓦。与之前的设计相比,所提出的设计在硬件资源利用率和速度性能之间实现了更好的权衡。
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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