A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers

IF 5.2 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-07 DOI:10.1109/TCSI.2024.3435696

Donggeon Kim;Yujin Choi;Jaewon Lee;Seoyoung Jang;Sungyu Song;Matthias Braendli;Thomas Morf;Marcel Kossel;Pier-Andrea Francese;Gain Kim

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引用次数: 0

Abstract

This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter (ADC)-based high-speed wireline receivers. The proposed technique breaks the loop-unrolled DFE (LU-DFE) chain by computing multiple LU-DFE chains in parallel with all possible seed symbols, and selecting the appropriate output by the post-processing selection logic. The proposed loop-break DFE (LB-DFE) is functionally equivalent to the conventional DFE with any other implementation techniques such as LU-DFE, look-ahead DFE (LA-DFE), or direct DFE. With topographical synthesis in 28nm CMOS process, the proposed LB-DFE achieved up to 54% of DFE area saving as compared to LA-DFE with look-ahead factor (LF) of 16 for 112Gb/s PAM-4 with 875MHz DSP clock speed. The implementation feasibility and functionality are verified using ZCU111 RFSoC platform at 6Gb/s (3GS/s ADC conversion rate) with a channel exhibiting 25dB loss at 1.5GHz, demonstrating the same bit error rate (BER) performance between the LB-DFE and the LA-DFE. Equipment-based measurements using arbitrary waveform generator (AWG) and real-time oscilloscope transmitting/receiving 40GBaud PAM-4 (80Gb/s) to/from the differential cables with software 21-tap feed-forward equalizer (FFE) and LB-DFE on PC was also conducted.

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用于基于 DAC/ADC-DSP 的有线收发器的断环决策反馈均衡器

本文提出了一种新型数字决策反馈均衡器（DFE）设计，可放宽基于模数转换器（ADC）的高速有线接收器的反馈时序限制。所提出的技术通过并行计算多个具有所有可能种子符号的 LU-DFE 链，并通过后处理选择逻辑选择适当的输出，从而打破了环路未滚动 DFE（LU-DFE）链。所提出的断环 DFE（LB-DFE）在功能上等同于采用任何其他实现技术（如 LU-DFE、前瞻 DFE（LA-DFE）或直接 DFE）的传统 DFE。通过在 28nm CMOS 工艺中进行拓扑合成，对于 875MHz DSP 时钟速度的 112Gb/s PAM-4，与前瞻因子（LF）为 16 的 LA-DFE 相比，所提出的 LB-DFE 实现了高达 54% 的 DFE 面积节省。使用 ZCU111 RFSoC 平台在 6Gb/s（3GS/s ADC 转换速率）速率下验证了实现的可行性和功能性，1.5GHz 时的信道损耗为 25dB，表明 LB-DFE 和 LA-DFE 具有相同的误码率 (BER) 性能。此外，还使用任意波形发生器（AWG）和实时示波器进行了基于设备的测量，使用软件 21 抽头前馈均衡器（FFE）和 PC 上的 LB-DFE 发送/接收 40GBaud PAM-4（80Gb/s）到/从差分电缆。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程：电子与电气

CiteScore

9.80

自引率

11.80%

发文量

441

审稿时长

2 months

期刊介绍： TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.