A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-07 DOI:10.1109/TVLSI.2024.3436575

Mehdi Saberi;Hossein Yaghoobzadeh Shadmehri;Mohammad Tavakkoli Ghouchani;Alexandre Schmid

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引用次数: 0

Abstract

This brief proposes a low-voltage, high-precision, and high-dynamic-range current-mode analog winner-take-all (WTA) circuit. The proposed structure employs a new high-gain stage as a feedback network between the input node of each cell and the common node of the circuit to reduce the sensitivity of the output current to the loser signals, especially when they are close to the winner. In addition, another network is employed that senses the amount of the output/winner current and adjusts the bias current of the gain stages. This ensures that the drain-source voltage of the input transistor in the winner cell matches the behavior of the output transistor’s drain-source voltage, enhancing the accuracy as well as the input dynamic range (DR) of the structure. Moreover, since the circuit works properly with a minimum supply voltage of only

$V_{\text {GS}} + V_{\text {eff}}$

, it is a promising candidate for applications in emerging technologies with low supply voltage requirements. Based on the proposed structure, a three-input WTA circuit is designed and fabricated in a 0.18-

$\mu $

m CMOS technology. According to the measurement results, the proposed circuit exhibits a maximum error of 1.5% for the input signal range of

$60~\mu $

A when the input frequency is 100 kHz. The silicon area occupied by the circuit is

$33~\mu $

$\times 65~\mu $

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用于低电压应用的高精度、高动态范围电流模式 WTA 电路

本简介提出了一种低电压、高精度和高动态范围的电流模式模拟赢家通吃（WTA）电路。所提出的结构采用了一个新的高增益级作为每个单元输入节点和电路公共节点之间的反馈网络，以降低输出电流对输家信号的敏感度，尤其是当输家信号接近赢家信号时。此外，还采用了另一个网络来检测输出/胜者电流的大小，并调整增益级的偏置电流。这确保了赢家单元中输入晶体管的漏极-源极电压与输出晶体管的漏极-源极电压相匹配，从而提高了结构的精度和输入动态范围 (DR)。此外，由于电路在最低电源电压仅为 $V_{\text {GS}} 的情况下也能正常工作。+ V_{\text {eff}}$，因此它有望应用于对电源电压要求较低的新兴技术中。根据所提出的结构，设计了一个三输入 WTA 电路，并在 0.18- $\mu $ m CMOS 技术中制作完成。测量结果表明，当输入频率为 100 kHz 时，输入信号范围为 $60~\mu $ A 时，所提电路的最大误差为 1.5%。电路所占用的硅面积为 33~\mu $ m，65~\mu $ m。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.