A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-09 DOI:10.1109/TVLSI.2024.3435974

Ziliang Zhou;Min Tan

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引用次数: 0

Abstract

This article proposes a high-efficiency all-nMOS bidirectional charge pump (CP) cell and constructs a CP-based high-voltage (HV) pulse driver based on it. Double-diode substrate isolation (DDSI) can extend the maximum supported voltage in a bulk CMOS process, but it requires an all-nMOS implementation of CP cells. Existing all-nMOS CPs either do not support the bidirectional charge transfer required for HV pulse drivers, or achieve it with additional penalties such as reversion charge loss and overstress on transistors. The proposed all-nMOS CP with novel gate voltage control strategies is the first one reported in the literature that can support the bidirectional charge transfer required for HV pulse drivers without suffering from reversion loss and threshold voltage loss or causing overstress on transistors. A ten-stage CP-based HV pulse driver is implemented in a 65-nm CMOS process utilizing this cell. Postlayout simulation results demonstrate that it can reliably generate 20-V HV pulses from a 2.5 V supply for a 15 pF // 200 k

$\Omega $

load at 55 kHz. The driver exhibits a peak power efficiency of 46.4% and occupies an area of 0.262 mm2.

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基于全 nMOS 充电泵的 20 V 脉冲驱动器，采用 65-nm 标准 CMOS 技术，无反向损耗和过应力

本文提出了一种高效率全 MOS 双向电荷泵 (CP) 单元，并在此基础上构建了基于 CP 的高压 (HV) 脉冲驱动器。双二极管基底隔离（DDSI）可以扩展体CMOS工艺的最大支持电压，但它需要CP单元的全MOS实现。现有的全非 MOS CP 要么不支持高压脉冲驱动器所需的双向电荷转移，要么在实现双向电荷转移时会产生额外的损失，如反向电荷损失和晶体管上的过应力。所提出的全 MOS CP 采用了新颖的栅极电压控制策略，是文献中首次报道的能够支持高压脉冲驱动器所需的双向电荷转移，同时不会出现回流损失和阈值电压损失，也不会对晶体管造成过应力。利用这种单元，在 65 纳米 CMOS 工艺中实现了基于 CP 的十级高压脉冲驱动器。布局后仿真结果表明，它能在 55 kHz 频率下可靠地从 2.5 V 电源为 15 pF // 200 k $\Omega $ 负载产生 20 V HV 脉冲。该驱动器的峰值功率效率为 46.4%，占地面积为 0.262 mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.